说明： VHDL写的51单片机内核，实现51的全部工能，学习开发FPGA的参考资料。
(VHDL wrote 51 microcontroller core, the realization of all the 51 workers may learn FPGA development of reference materials.)
文件列表：
core51
......\actgen
......\constraint
......\core51.prj
......\designer
......\........\impl1
......\........\.....\impl.prj_des
......\........\.....\simulation
......\........\.....\..........\postlayout
......\hdl
......\...\addsub_core_.vhd
......\...\addsub_core_struc.vhd
......\...\addsub_core_struc_cfg.vhd
......\...\addsub_cy_.vhd
......\...\addsub_cy_rtl.vhd
......\...\addsub_cy_rtl_cfg.vhd
......\...\addsub_ovcy_.vhd
......\...\addsub_ovcy_rtl.vhd
......\...\addsub_ovcy_rtl_cfg.vhd
......\...\alucore_.vhd
......\...\alucore_rtl.vhd
......\...\alucore_rtl_cfg.vhd
......\...\alumux_.vhd
......\...\alumux_rtl.vhd
......\...\alumux_rtl_cfg.vhd
......\...\comb_divider_.vhd
......\...\comb_divider_rtl.vhd
......\...\comb_divider_rtl_cfg.vhd
......\...\comb_mltplr_.vhd
......\...\comb_mltplr_rtl.vhd
......\...\comb_mltplr_rtl_cfg.vhd
......\...\control_fsm_.vhd
......\...\control_fsm_rtl.vhd
......\...\control_fsm_rtl_cfg.vhd
......\...\control_mem_.vhd
......\...\control_mem_rtl.vhd
......\...\control_mem_rtl_cfg.vhd
......\...\dcml_adjust_.vhd
......\...\dcml_adjust_rtl.vhd
......\...\dcml_adjust_rtl_cfg.vhd
......\...\mc8051_alu_.vhd
......\...\mc8051_alu_struc.vhd
......\...\mc8051_alu_struc_cfg.vhd
......\...\mc8051_control_.vhd
......\...\mc8051_control_struc.vhd
......\...\mc8051_control_struc_cfg.vhd
......\...\mc8051_core_.vhd
......\...\mc8051_core_struc.vhd
......\...\mc8051_core_struc_cfg.vhd
......\...\mc8051_p.vhd
......\...\mc8051_siu_.vhd
......\...\mc8051_siu_rtl.vhd
......\...\mc8051_siu_rtl_cfg.vhd
......\...\mc8051_tmrctr_.vhd
......\...\mc8051_tmrctr_rtl.vhd
......\...\mc8051_tmrctr_rtl.vhd~
......\...\mc8051_tmrctr_rtl_cfg.vhd
......\...\mc8051_top_.vhd
......\...\mc8051_top_struc.vhd
......\...\mc8051_top_struc_cfg.vhd
......\package
......\phy_synthesis
......\simulation
......\..........\meminit.dat
......\..........\modelsim.ini
......\stimulus
......\synthesis
......\viewdraw
......\........\sch
......\........\sym
......\........\vf
......\........\..\project.lst
......\........\viewdraw.ini
......\........\wir
