FPGACPLD

说明：  在数字电路的设计中，时序设计是一个系统性能的主要标志，在高层次设计方法中，对时序控制的抽象度也相应提高，因此在设计中较难把握，但在理解RTL电路时序模型的基础上，采用合理的设计方法在设计复杂数字系统是行之有效的，通过许多设计实例证明采用这种方式可以使电路的后仿真通过率大大提高，并且系统的工作频率可以达到一个较高水平
(In digital circuit design, timing design is a main indicator of system performance in high-level design methods, control of timing was also a corresponding increase in the abstract, so more difficult to grasp in the design, but in understanding the RTL circuit timing model based on rational design methods used in the design of complex digital systems is a well-established through many design examples prove that this approach can make the circuit after the simulation significantly improve pass rates, and the system operating frequency can reach a high level)