所属分类：
其他
开发工具：Verilog
文件大小：617KB
下载次数：11
上传日期：2017-08-04 16:44:00
说明： ad转换器ads822e/ads822的驱动模块
(AD converter ads822e/ads822 driver module)
文件列表：
ADS822E\AD(ADS822E)模块(原理图).pdf
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.asm.rpt
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.done
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.fit.rpt
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.fit.smsg
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.fit.summary
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.flow.rpt
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.map.rpt
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.map.summary
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.pin
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.pof
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.qpf
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.qsf
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.qws
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.sof
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.tan.rpt
ADS822E\ad1_da1_test(Altera_Verilog)\ad1_da1_test.tan.summary
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.asm.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cbx.xml
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.bpm
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.ecobp
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.hdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.kpt
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.logdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.rdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp.tdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp0.ddb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.cmp_merge.kpt
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.db_info
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.eco.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.fit.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.hier_info
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.hif
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.lpc.html
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.lpc.rdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.lpc.txt
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.bpm
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.ecobp
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.hdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.kpt
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.logdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map_bb.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map_bb.hdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.map_bb.logdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.pre_map.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.pre_map.hdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.rtlv.hdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.rtlv_sg.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.rtlv_sg_swap.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.sgdiff.cdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.sgdiff.hdb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.sld_design_entry.sci
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.sld_design_entry_dsc.sci
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.syn_hier_info
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.tan.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.tis_db_list.ddb
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test.tmw_info
ADS822E\ad1_da1_test(Altera_Verilog)\db\ad1_da1_test_global_asgn_op.abo
ADS822E\ad1_da1_test(Altera_Verilog)\db\add_sub_und.tdf
ADS822E\ad1_da1_test(Altera_Verilog)\db\altsyncram_n831.tdf
ADS822E\ad1_da1_test(Altera_Verilog)\db\cmpr_k4c.tdf
ADS822E\ad1_da1_test(Altera_Verilog)\db\cntr_2df.tdf
ADS822E\ad1_da1_test(Altera_Verilog)\db\prev_cmp_ad1_da1_test.asm.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\prev_cmp_ad1_da1_test.fit.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\prev_cmp_ad1_da1_test.map.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\prev_cmp_ad1_da1_test.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\prev_cmp_ad1_da1_test.tan.qmsg
ADS822E\ad1_da1_test(Altera_Verilog)\db\shift_taps_4ql.tdf
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.cmp.atm
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.cmp.dfp
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.cmp.hdbx
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.cmp.kpt
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.cmp.logdb
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.cmp.rcf
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.map.atm
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.map.dpi
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.map.hdbx
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions\ad1_da1_test.root_partition.map.kpt
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\README
ADS822E\ad1_da1_test(Altera_Verilog)\topdesign.v
ADS822E\ad1_da1_test(Altera_Verilog)\topdesign.v.bak
ADS822E\ad1_da1_test(Altera_Verilog).rar
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db\compiled_partitions
ADS822E\ad1_da1_test(Altera_Verilog)\db
ADS822E\ad1_da1_test(Altera_Verilog)\incremental_db
ADS822E\ad1_da1_test(Altera_Verilog)
ADS822E
