所属分类:
行业发展研究
开发工具:VHDL
文件大小:74KB
下载次数:2
上传日期:2009-04-29 04:52:40
说明: DDS divider clock AHDL
文件列表:
fr_div
......\cmp_state.ini
......\db
......\..\fr_div-sim.vwf
......\..\fr_div.csf.msg
......\..\fr_div.db_info
......\..\fr_div.fr_div.csf.hdb
......\..\fr_div.fr_div.csf.rdb
......\..\fr_div.fr_div.db_entries.csf.cdb
......\..\fr_div.fr_div.sgate_entries.csf.cdb
......\..\fr_div.fr_div.sgate_entries.csf.hdb
......\..\fr_div.fr_div.ssf.hdb
......\..\fr_div.fr_div.ssf.rdb
......\..\fr_div.fr_div.tdb_netlist.csf.tdb
......\..\fr_div.fr_div.tim_manager.csf.ddb
......\..\fr_div.hif
......\..\fr_div.psf.hdb
......\..\fr_div.ssf.msg
......\..\fr_div_hier_info
......\..\fr_div_syn_hier_info
......\debug.fsf
......\fr_div.csf
......\fr_div.csf.rpt
......\fr_div.eqn
......\fr_div.pin
......\fr_div.pof
......\fr_div.psf
......\fr_div.quartus
......\fr_div.qws
......\fr_div.sof
......\fr_div.ssf
......\fr_div.ssf.rpt
......\fr_div.tdf
......\fr_div.vwf
......\release.fsf