说明： The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and verification of a digital UART (Universal
Asynchronous Receiver & Transmitter).
