DPLL_Circuit

说明：  本文在说明全数字锁相环的基础上，提出了一种利用FPGA设计一阶全数字锁相环的方法，并 给出了关键部件的RTL可综合代码，并结合本设计的一些仿真波形详细描述了数字锁相环的工作过程，最后对一些有关的问题进行了讨论。
(In this paper, that all-digital phase-locked loop based on a FPGA design using first-order DPLL method, and gives the key components of the RTL code can be integrated and combined with the design of some of the detailed simulation waveform describes the working process of digital phase-locked loop, the last of some related issues were discussed.)