fpga_fifo_0122_02
.................
\component
.................
\constraint
.................
\coreconsole
.................
\designer
.................\........
\impl1
.................\........\.....
\simulation
.................\........
\impl2
.................\........\.....\designer_genhdl.
log
.................\........\.....\fpga_core.
tcl
.................\........\.....
\simulation
.................
\hdl
.................\...\fifo_fpga_1280x8.
v
.................\...\fifo_fpga_1280x8.v.
bak
.................\new.
prj
.................
\phy_synthesis
.................
\simulation
.................\..........\fifo_fpga_R0C0.
mem
.................\..........\fifo_fpga_R1C0.
mem
.................\..........\fifo_fpga_R2C0.
mem
.................\..........\meminit.
dat
.................\..........\modelsim.
ini
.................\..........\modelsim.ini.
sav
.................\..........\modelsim.
log
.................\..........
\presynth
.................\..........\........
\ctr_data_tb
.................\..........\........\...........\verilog.
psm
.................\..........\........\...........\_primary.
dat
.................\..........\........\...........\_primary.
vhd
.................\..........\........
\fifo_fpga
.................\..........\........\.........\verilog.
psm
.................\..........\........\.........\_primary.
dat
.................\..........\........\.........\_primary.
vhd
.................\..........\........
\fifo_fpga1280x8
.................\..........\........\...............\verilog.
psm
.................\..........\........\...............\_primary.
dat
.................\..........\........\...............\_primary.
vhd
.................\..........\........
\fpga_core
.................\..........\........\.........\verilog.
psm
.................\..........\........\.........\_primary.
dat
.................\..........\........\.........\_primary.
vhd
.................\..........\........
\fpga_core_tb
.................\..........\........\............\verilog.
psm
.................\..........\........\............\_primary.
dat
.................\..........\........\............\_primary.
vhd
.................\..........\........
\fpga_fpga_1280x8_tb
.................\..........\........\...................\verilog.
psm
.................\..........\........\...................\_primary.
dat
.................\..........\........\...................\_primary.
vhd
.................\..........\........\
_info
.................\..........\........
\_temp
.................\..........\recv_data.
dat
.................\..........\rec_data.
dat
.................\..........\run.
do
.................\..........\uart_send_data.
dat
.................\..........\uart_send_data.dat.
bak
.................\..........\vsim.
wlf
.................
\smartgen
.................\........
\clk_pll
.................\........\.......\clk_pll.
cxf
.................\........\.......\clk_pll.
gen
.................\........\.......\clk_pll.
log
.................\........\.......\clk_pll.
v
.................\........\clk_pll_work.
ixf
.................\........
\fifo_fpga
.................\........\.........\fifo_fpga.
shx
.................\........\.........\fifo_fpga_R0C0.
mem
.................\........\.........\fifo_fpga_R1C0.
mem
.................\........\.........\fifo_fpga_R2C0.
mem
.................\........
\fifo_fpga1280x8
.................\........\...............\fifo_fpga1280x8.
cxf
.................\........\...............\fifo_fpga1280x8.
gen
.................\........\...............\fifo_fpga1280x8.
log
.................\........\...............\fifo_fpga1280x8.
v
.................\........\fifo_fpga1280x8_work.
ixf
.................\........\smartgen.
aws
.................
\stimulus
.................\........\BtimErrors.
log
.................\........\ctr_data_tb.
v
.................\........\ctr_data_tb.v.
bak
.................\........\fifo_fpga_1280x8_tb.
v
.................\........\files_to_build.
txt
.................\........\fpga_core.
dsk
.................\........\fpga_core.
hpj
.................\........\fpga_core_tb.
v
.................\........\fpga_core_tb.v.
bak
.................\........\waveperl.
log
.................
\synthesis
.................\.........\.
recordref
.................\.........
\backup
.................\.........\......\fpga_core.
srr
.................\.........\fpga_core.
areasrr
.................\.........\fpga_core.
edn
.................\.........\fpga_core.
map
.................\.........\fpga_core.
sdf
.................\.........\fpga_core.
srd
.................\.........\fpga_core.
srm
.................\.........\fpga_core.
srr
.................\.........\fpga_core.
srs
.................\.........\fpga_core.
tlg
