用FPGA模拟VGA时序、模拟PS 2总线的键盘接口VHDL源代码
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\S3Demo
...................................................\......\automake.
log
...................................................\......\
bitgen.ut
...................................................\......\coregen.
log
...................................................\......\coregen.
prj
...................................................\......\
kb2vhdl.vhd
...................................................\......\README.
txt
...................................................\......\README.
txt~
...................................................\......\
s3demo.bgn
...................................................\......\s3demo.
bit
...................................................\......\
s3demo.bld
...................................................\......\s3demo.
cmd_log
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S3demo.dhp
...................................................\......\s3demo.
drc
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S3demo.lfp
...................................................\......\s3demo.
lso
...................................................\......\S3demo.
mcs
...................................................\......\
s3demo.mrp
...................................................\......\s3demo.
nc1
...................................................\......\s3demo.
ncd
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s3demo.ngc
...................................................\......\
s3demo.ngd
...................................................\......\s3demo.
ngm
...................................................\......\
s3demo.ngr
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S3demo.npl
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s3demo.pad
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s3demo.pad_txt
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s3demo.par
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s3demo.pcf
...................................................\......\s3demo.
placed_ncd_tracker
...................................................\......\s3demo.
prj
...................................................\......\
S3demo.prm
...................................................\......\s3demo.
routed_ncd_tracker
...................................................\......\
S3demo.sig
...................................................\......\s3demo.
stx
...................................................\......\
s3demo.syr
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s3demo.twr
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s3demo.twx
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S3demo.ucf
...................................................\......\S3demo.ucf.
untf
...................................................\......\
s3demo.ut
...................................................\......\
S3demo.vhd
...................................................\......\s3demo.
xpi
...................................................\......\s3demo_cclktemp.
bit
...................................................\......\s3demo_last_par.
ncd
...................................................\......\s3demo_map.
ncd
...................................................\......\s3demo_map.
ngm
...................................................\......\
s3demo_pad.csv
...................................................\......\s3demo_pad.
txt
...................................................\......\
vga_main.vhd
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\xst
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\work
...................................................\......\...\....\
hdllib.ref
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hdpdeps.ref
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\sub00
...................................................\......\...\....\.....\vhpl00.
vho
...................................................\......\...\....\.....\vhpl01.
vho
...................................................\......\...\....\.....\vhpl02.
vho
...................................................\......\...\....\.....\vhpl03.
vho
...................................................\......\...\....\.....\vhpl04.
vho
...................................................\......\...\....\.....\vhpl05.
vho
...................................................\......\...\....\.....\vhpl06.
vho
...................................................\......\...\....\.....\vhpl07.
vho
...................................................\......\_impact.
cmd
...................................................\......\_impact.
log
...................................................\......
\_ngo
...................................................\......\....\netlist.
lst
...................................................\......\
_pace.ucf
...................................................\......
\__projnav
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bitgen.rsp
...................................................\......\.........\coregen.
rsp
...................................................\......\.........\ednTOngd_tcl.
rsp
...................................................\......\.........\map.
log
...................................................\......\.........\nc1TOncd_tcl.
rsp
...................................................\......\.........\par.
log
...................................................\......\.........\
pegasusdemo.xst
...................................................\......\.........\pegasusdemo_ncdTOut_tcl.
rsp
...................................................\......\.........\posttrc.
log
...................................................\......\.........\runXst_tcl.
rsp
...................................................\......\.........\
S3demo.gfl
...................................................\......\.........\
s3demo.xst
...................................................\......\.........\
S3demo_flowplus.gfl
...................................................\......\.........\s3demo_ncdTOut_tcl.
rsp
...................................................\......\__projnav.
log
...................................................\使用说明请参看右侧注释====〉〉.
txt