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FPGA-I2C

价格: ¥ 9 积分可抵¥ 9

最后更新: 2019-12-24 16:27:22

演示地址:

指导费: 免费

分类
参数1
参数2
参数3
参数4
参数5
参数6
大小
1 MB
发货方式
自动发货
下载方式
远程下载
1
1
1
备注说明

所属分类串口编程
开发工具:MultiPlatform
文件大小:229KB
下载次数:126
上传日期:2006-03-10 22:51:26
说明:  利用FPGA 编程实现I2C总线,对学习很有帮助
(FPGA Programming I2C bus, a pair of useful learning)

文件列表
I2C
...\automake.log
...\Chapter7 Sample
...\...............\LWBBUSCHANGE.v
...\...............\LWBDECODE.v
...\...............\LWBDECODE.v.bak
...\...............\LWBSAA7113.v
...\...............\LWBSRAM.v
...\...............\timescale.v
...\...............\tst_saa7113.v
...\...............\使用说明.txt
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\I2C.npl
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl.v.bak
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl.v.bak
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_defines.v.bak
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top.v.bak
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\i2c_slave_model.v.bak
...\I2C源代码
...\.........\i2c_master_bit_ctrl.txt
...\.........\i2c_master_byte_ctrl.txt
...\.........\i2c_master_defines.txt
...\.........\i2c_master_top.txt
...\.........\i2c_slave_model.txt
...\.........\timescale.txt
...\.........\tst_bench_top.txt
...\.........\wb_master_model.txt
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\wb_master_model.v.bak
...\work
...\....\glbl
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\i2c_slave_model
...\....\...............\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\_info
...\xst
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg07
...\...\....\.....\i2c_master_bit_ctrl.bin
...\...\....\vlg5C
...\...\....\.....\i2c_master_byte_ctrl.bin
...\...\....\vlg67
...\...\....\.....\i2c_master_top.bin
...\__projnav
...\.........\coregen.rsp
...\.........\I2C.gfl
...\.........\I2C_flowplus.gfl
...\.........\i2c_master_bit_ctrl.xst
...\.........\i2c_master_byte_ctrl.xst
...\.........\i2c_master_top.xst
...\.........\runXst_tcl.rsp
...\.........\xst_sprjTOstx_tcl.rsp
...\__projnav.log

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